postech wcu


Nano Sensor and Systems

Nano Sensor and Systems
Prof. Hong June Park님의 사진입니다.
Prof. Hong June Park
E-Mail :
Position : Professor
Tel. : +82-54-279-2234, Lab: +82-54-279-5025
Laboratory : Analog IC Systems Lab.
Office : LG Bldg. #417
- Ph.D. in Electrical Engineering University of California, Berkeley (1989)
- M.S. in Electrical Engineering, KAIST, Taejon, Korea (1981)
- B.S. in Electrical Engineering, Korea University, Seoul, Korea (1979)
- CAD engineer in ETRI, Korea (1981-1984)
- Senior Engineer in the TCAD Department of Intel (1989-1991)
- Professor, Electronic and Electrical Engineering, POSTECH (1991 - Present)
- Wireline Committee Member, International Solid-State Circuits Conference
- Editor, Journal of Semiconductor Technology and Science
- Multi-giga bps CMOS interface system design
- Multi-drop interface circuits (Memory)
- Point-to-point interface circuits (LCD driver, USB 3.0 PHY)
- Signal integrity, crosstalk, channel modeling
- Mixed-mode circuit simulation for mluti-core CPU
- Low-power analog-digital mixed-mode circuit design
- “A Serpentine-Shaped Microstrip Lines with Zero Far-End Crosstalk for Parallel High-Speed DRAM Interface”, Kyoungho Lee, Hae-Kang Jung, Hyung-Joon Chi, Hye-Jung Kwon, Jae-Yoon Sim, and Hong-June Park, accepted for publication, IEEE Trans. Advanced Packaging
- "A 2Gb/s CMOS Integrating 2-tap DFE Receiver for Four-drop Single-ended Signaling", Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park, IEEE Transactions on Circuits and systems-I, 2008 accepted for publication
- "A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB 2.0 High-Speed Interface", Sang-Hune Park, Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park, IEEE Transactions on Circuits and systems-II, Vol.55, No.2, pp.156-160, Feb.2008
- "A VCDL-based 60-760MHz Dual-Loop DLL with Infinite Phase Shift Capabilty and Adaptive Bandwidth Scheme", Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Hong-June Park , IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.40, No.5 p.1119~1129, May 2005
- “A CMOS Digital Duty Cycle Correction Circuit for Multi-Phase Clock”, Young-Chan Jang, Seung-Jun Bae and Hong-June Park, IEE Electronics Letters 18th September 2003 Vol.39 No.19