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75 J. Kim, H. Oh, J. Kim, R.-H. Baek, J.-W. Han, M. Meyyappan, and J.-S. Lee, Journal of Vacuum Science & Technology B, (Accepted), 2017 
74 H. Lee, J. Lee, S. Baek, W. H. Jeong, Y. Lee, T. Yang, and J.-S. Lee, IEEE Electron Device Letters, vol. 38, no. 2, pp. 187-190, Feb. 2017 
73 S. Baek, J. Lee, I. Park, and J.-S. Lee, R.H. Baek, and J. S. Lee, Solid-State Electronics, Oct 2017. 
72 H. Lee, J. Lee, H. Oh, M. Meyyappan, J. Kim and J.-S. Lee, Journal of Nanoscience and Nanotechnology , vol. 17, No. 5., May, 2017 
71 J. Kim, H. Oh, J. Kim, M. Meyyappan, and J.-S. Lee, Japanese Journal of Applied Physics, vol. 56, No. 2. Jan, 2017 
70 N. Hong, C. Park, D. Kim, M. Meyyappan, and J.-S. Lee, Sensors and Actuators B Chemical, vol. 242, pp 324-331, April 2017 
69 H. Oh, J. Kim, J. Lee, T. Rim, C. –K. Baek, and J. –S. Lee, “Effects of single grain boundary and random interface traps on electrical variations of sub-30nm polysilicon nanowire structures”, Microelectronic Engineering, vol. 149, no. 5, pp. 113, Jan. 2016 
68 K. Kim, C. Park, D. Kwon, D. Kim, M. Meyyappan, S. Jeon, and J. –S. Lee, “Silicon nanowire biosensors for detection of cardiac troponin I (cTnI) with high sensitivity”, Biosensors and Bioelectronics, vol. 77, pp. 695, Mar. 2016 
67 J. Kim, H. Oh, J. Lee, C.-K. Baek, M. Meyyappan, and J.-S. Lee, “Three-dimensional simulation of threshold voltage variations due to an oblique single grain boundary in sub-40nm polysilicon nanowire FETs”, Semiconductor Science and Technology, vol. 30, no. 
66 J. H. Hong, S. H. Lee, Y. R. Kim, E. Y. Jeong, J. S. Yoon, J. –S. Lee, R. H. Baek, and Y. H. Jeong, “Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs”, Japanese Jour