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127 E. Y. Jeong et al., 'Investigation of RC Parastics Considering Middel-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications,' IEEE Transactions on Electron Devices, vol. 62, no. 10, Oct. 2015.  -
126 J. S. Yoon et. al., 'Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node,' IEEE Electron Device Letters, vol. 36. no. 10. Oct. 2015  -
125 S. Sakong, S. H. Lee, T. Rim, Y. W. Jo, J. H. Lee, and Y. H. Jeong, '1/f Noise Characteristics of Surface-Treated Normally-Off Al2O3/GaN MOSFETs,' IEEE Electron Device Letters, vol. 36, no. 3, Mar. 2015  -
124 E. Y. Jeong et al., 'Physical DC and thermal noise models of 18nm double-gate junctionless p-type MOSFETs for low noise RF applications,' Japanese Journal of Applied Physics, vol. 54, no. 4, pp. 04DC08, Apr. 2015.  -
123 J. H. Hong et al., 'Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs,' Japanese Journal of Applied Physics, vol. 54, no. 4, pp. 04DN05, Apr. 2015.  -
122 J. S. Yoon et. al., “Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors,” Applied Physics Letters, vol. 106, no. 10, pp. 103507, Mar. 2015.  -
121 J. W. Jang, S. Park, G. W. Burr, H. Hwang, and Y. H. Jeong, 'Optimization of Conductance Change in Pr1-xCaxMnO3-based Synaptic Devices for Neuromorphic System,' IEEE Electron Device Letters, Vol. 36, No. 5, May. 2015.  -
120 J. S. Yoon, E. Y. Jeong, S. H. Lee, Y. R. Kim, J. H. Hong, J. S. Lee, and Y. H. Jeong, 'Extraction of source/drain resistivity parameters optimized for double-gate FinFETs,' Japanese Jounal of Applied Physics, vol. 54, no. 4S, pp.04DC06, Apr. 2015.  -
119 S. H. Lee et. al., 'Investigation of Low-Frequency Noise in p-type Nanowire FETs: Effect of Switched Biasing Condition and Embedded SiGe Layer,' IEEE Electron Device Letters, vol. 35, no. 7, Jul. 2014.  -
118 J. S. Yoon, T. Rim, J. Kim, M. Meyyappan, C. K. Baek, and Y. H. Jeong, 'Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths,' Applied Physics Letters, vol. 105, no. 10, pp. 102105, Sep. 2014.  -
117 T. Rim, K. Kim, S. Kim, C. K. Baek, M. Meyyappan, Y. H. Jeong, and J. S. Lee, 'Improved Electrical Characteristics of Honeycomb Nanowire ISFETs,' IEEE Electron Device Letters, vol. 34, no. 8, Aug. 2013.  -
116 T. Rim et al., 'Investigation of the electrical stability of Si-nanowire biologically sensitive field-effect transistors with embedded Ag/AgCl pseudo reference electrode,' RSC Advances, vol. 3, pp. 7963-7969, Mar. 2013.  -
115 M. S. Park et al., 'Reliability study of methods to suppress boron transient enhanced diffusion in high-k/metal gate Si/SiGe channel pMOSFETs,' Microelectronic Engineering, vol. 112, pp. 80-83, Jun. 2013.  -
114 M. D. Ko, C. W. Sohn, C. K. Baek, and Y. H. Jeong, "Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis," IEEE Trans. Electron Devices, vol. 60, no. 9, pp. 2721-2727, Sep. 2013.  -
113 Y. R. Kim, S. H. Lee, C. W. Sohn, D. Y. Choi, H. C. Sagong, S. Kim, E. Y. Jeong, D. W. Kim, H. Hong, C. K. Baek, J. S. Lee, D. M. Kim, and Y. H. jeong, "Simple S/D Series Resistance Extraction Method Optimized for Nanowire FETs", IEEE Electron Device Letters, vol. 34, no. 7, pp. 828-830, Jul. 2013  -