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Flexible, organic, printed nanoelectronic devices

Flexible organic thin film memory devices

Flexible organic memory devices

(a) Three-dimensional schematic diagram of the memory device architecture. Patterned Ti/Au on the PES plastic substrate was used as the gate electrode and the cross-linked PVP layers were used as the blocking and tunneling organic dielectric layers. The self-assembled AuNP charge storage layers were formed on the APTES-coated PVP blocking dielectric layer. The pentacene active layer and the gold source/ drain contacts were formed to make the organic transistor-based memory devices. The chemical structures of the organic layers are shown in the figure. (b) Photograph of the fabricated flexible organic memory devices. (The device size is 3 × 3 cm2.)

Oxide semiconductor devices

Oxide semiconductor devices

(a) The schematic illustration of the device structure, (b) cross sectional TEM image of the fabricated device, and (c) photograph of the a -HIZO TFTs that were integrated on the 6-inch glass wafer and a magnified image of the TFT (inset).