Self-assembled materials and devices

Bottom-up : self-assembly

Bottom-up: Self-assembly

Fabrication of nano-masks


Schematic diagram of the experimental processes for the fabrication of nanoporous alumina template layers. (a) Anodized aluminum oxide (AAO) nanotemplate (reference template), (b) pore size control of the AAO nanotemplates (left: reducing the pore size by depositing a thickneSchematic diagram of the experimental processes for the fabrication of nanoporous alumina template layers. (c) application of polystyrene (PS) inside the AAO template, (d) detachment of the PS/AAO templates from the Al sheets, and (e) removal of the barrier layers.


Schematic illustration of the fabrication processes for the arrays of nanodot resistive switching memory elements using the pore-size-controlled AAO nanotemplates. (a) Polystyrene (PS)-filled AAO masks placed on the substrates with bottom electrodes. (b) Removal of the PS layer from the AAO masks. (c) Schematic process steps to fabricate nanoscale resistive switching memory devices by using AAO masks.

  1. Three-dimensional view of the AAO nanotemplates placed on the substrates.
  2. Deposition of a HfO2 thin film on the substrate with an AAO nanotemplate mask.
  3. Deposition of the Au top electrode on the HfO2 nanodot array/substrate with an AAO nanotemplate mask.
  4. By removing the AAO mask, arrays of Au/HfO2 nanodots can be formed on the substrate, resulting in nanoscale resistive switching memory device elements with a structure of Au (top electrode)/HfO2/Pt (bottom electrode).

Scalable nano-sized masks and nanodots

nano dots

Fabrication of nanodots using AAO nanotemplates. (a) Plan view of the FE-SEM images of the AAO masks on the conductive substrate with a controlled AAO pore size from around 25 nm to 95 nm. (b) Plan view of the FE-SEM images of the HfO2 nanodots with a controlled dot size of approximately 24 to 91 nm. (c) Plot of the template size versus the dot size calculated from Figures 3(a) and (b). The scale bars in Figs. 3(a) and 3(b) are 200 nm.

Self-assembled memory devices

Self-assembled memory devices

Nanoscale device characterization

Nanoscale device characterization

(a) Schematic illustration of the current-sensing atomic force microscopy set-up for measuring the resistive switching characteristics. (b) The resistive switching characteristics of the nanoscale resistive switching memory device with a memory size of around 2.01×10-11 cm2. (c) The current-voltage responses of the sample with an AFM probe that was directly attached to the bottom electrode (short circuit) or that did not contact the top electrode (open circuit) to determine the validity of using the AFM probe for electrical biasing. (d) A cumulative probability data set obtained by measuring 65 resistive switching memory devices. The current levels for the high-resistance (HRS) and low-resistance states (LRS) states measured at a reading bias of 2 V. (e) The histogram of the set/reset voltages for 65 devices.