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Nanostructured nonvolatile memory devices

Nonvolatile memory devices

Nonvolatile memory devices image

Schematic illustration of memory architectures and storage element configurations. Elemental metal nanoparticles of Co and Au and a binary mixture thereof, which were synthesized by plasma treatment on PS-b-P4VP micelles loaded with CoCl2 and HAuCl4, and a binary mixture of micelles loaded with two compounds independently, were used as charge-trapping layers. A sputter-deposited HfO2 layer was used both as a tunneling (thickness of 5 nm) and blocking oxide layer (thickness of 15 nm). A high-work function metal gate of Pt was used as a gate electrode. Instead of images of nanoparticles after plasma treatment, TEM images of PS-b-P4VP micelles loaded with CoCl2 and HAuCl4 were displayed because micelles with CoCl2 and HAuCl4 were clearly distinguishable in the images.

Nano-scale

Nano-scale
Nano-scale